1. Field of the Invention
The present invention relates to a semiconductor device having an interconnect and, more particularly, to a semiconductor device which is suitable for use in various semiconductor technologies requiring high degrees of integration and fineness of semiconductors.
2. Description of Related Art
In the field of semiconductor technology, there is a trend towards a greater scale of integration of semiconductor devices, requiring shallower interconnect structures and, at the same time, finer contact holes with greater depths.
A description will now be given, by way of example, as to a semiconductor process, and particularly to production of a MOSFET, with specific reference to FIGS. 12 to 14.
Step (a):
Referring first to FIG. 12, a device isolation region 12 (local oxidation of silicon, referred to as "LOCOS SiO.sub.2 ") and a gate region are formed on a semiconductor substrate (silicon) denoted by 1. The gate region includes a gate material 15 (polysilicon, polycide or the like), a gate insulation film 17 (SiO.sub.2) and a gate side wall denoted by 16a, 16b. This structure is obtained by effecting ion implantation to form a lightly doped drain region (referred to as "LDD region") 14a, 14b, forming the gate side wall 16a, 16b, and effecting ion implantation to form source/drain regions 13a, 13b.
Step (b):
Then, an interlayer insulator 18 is formed by, for example, a spin-on-glass technique (referred to as "SOG"), chemical vapor deposition (referred to as "CVD") of SiO.sub.2, or SiO.sub.2 formation by using TEOS (Si(OC.sub.2 H.sub.5).sub.4), followed by formation of a wiring contact hole 19, whereby a structure as shown in FIG. 13 is obtained.
Step (c):
Then, a TiN/Ti laminate film is laid by sputtering and a metal plug 23 as an embedded contact material is formed. In this case, tungsten (W) is used as the buried material 23. Then, although not shown, a dual layer of Al-Si/Ti is deposited over the whole surface, followed by a patterning. The TiN/Ti layer underlying W is designated by numeral 20. A wiring region is thus formed, whereby a structure as shown in FIG. 14 is obtained.
In the process described above, it is necessary to remove, in advance of the formation of the metal plug 23 in the contact hole 19, the native oxide film formed on the silicon (Si) substrate 1. The removal of such an oxide film is typically performed by using diluted fluoric acid. However, the aforementioned trend towards a greater degree of fineness and a higher aspect ratio of the contact hole 19 makes it difficult to charge the contact hole 19 with diluted fluoric acid of a quantity large enough to remove the native oxide film inside the contact hole, resulting in imperfect removal of the oxide film. This causes an imperfect filling of the contact hole 19, allowing defects such as the generation of voids, thus causing a failure to provide satisfactory ohmic contact between the metal plug 23 and the silicon substrate which serves as a semiconductor layer, resulting in an increase in the wiring resistance. Since the interlayer insulator 18 in which the contact hole 19 is formed is mainly constituted by an oxide film, the interlayer insulator 18 also is etched isotropically during the treatment with the diluted fluoric acid, tending to reduce the thickness of the interlayer insulator 18. Such an isotropic etching effect also enlarges the contact hole 19, thus causing an impediment to the controllability of delicate and fine processing.
A non-wet etching technique using, for example, hydrogen fluoride (referred to as "HF") vapor has been proposed and discussed as being one measure for eliminating these problems. However, etching relying on HF vapor is basically a chemical reaction and, hence, proceeds isotropically as in the case of wet etching. This solution therefore is ineffective in prevention of enlargement of the contact hole 19. A problem is caused when the underlying interlayer insulator is formed of SOG or the like. Namely, in such a case, the SOG which is exposed on the side face of the contact hole 19 is etched preferentially because SOG exhibits a greater etching rate than other oxide films. Consequently, the contact hole 19 after the treatment with the HF vapor exhibits local deformation at the portion where SOG exists, so that the embedded contact material, which is formed after the treatment, tends to be stepped or made discontinuous, resulting in a reduced coverage.
A technique referred to as a dry pre-processing method has also been proposed and discussed. In order to achieve etching anisotropy, it is important to introduce a certain degree of ion etching component into the etching process. However, high ion energy tends to damage silicon, in particular underlying shallow junctions, allowing an increase in junction leakage current. One of the effective measures for solving this problem is to effect an etching in such a manner as not to cause damage on the underlying substrate. It has also been proposed to conduct a soft-etching pre-processing by using a high-density plasma generated by, for example, an inductively coupled plasma (referred to as "ICP") device, in an inert gas atmosphere with or without introduction of a reactive gas. The mechanisms of these methods, however, are still unclear and, therefore, optimum conditions for achieving stable ohmic contacts have not yet been established. All these proposed methods are thus still unsatisfactory in that they cannot meet required levels of stability both in electrical characteristics and the yield of interconnects in the semiconductor devices. Under these circumstances, there is a strong demand for clarification of mechanisms and conditions for achieving stable ohmic contacts in order to obtain a wiring contact structure which can overcome the above-described problems, as well as a method for realizing such a wiring contact structure.
Besides the described pre-processing techniques conducted prior to the formation of the metal plug, it is also an effective technique to form an underlying contacting layer which underlies the conductive material to be embedded, e.g., a W-based material, in order to achieve a stable ohmic contact. For instance, a thick Ti layer as an underlying contacting layer deposited in a contact hole reduces and thus removes native oxide film on the Si so as to achieve a stable contact. However, too large a thickness of the underlying layer decreases the contact hole diameter available for embedding the W-based material such as a blanket tungsten, making it difficult to stably embed the blanket tungsten after the deposition of the underlying contact layer. A similar problem is caused also when the thickness of a titanium nitride (TiN) used as a barrier metal is large. These problems are attributable to the fact that optimum conditions for the underlying contacting layer and, hence, optimum blanket tungsten structure, have not yet been established.